`timescale 1ns/1ps

module uart_byte_rx_tb();
	reg Clk;
	reg Reset_n;
	reg uart_rx;
	wire Rx_Done;
	wire [7:0] Rx_Data;
	
uart_byte_rx uart_byte_rx(
		.Clk(Clk),
		.Reset_n(Reset_n),
		.uart_rx(uart_rx),
		.Rx_Done(Rx_Done),
		.Rx_Data(Rx_Data)
);

	initial Clk = 1;
	always #10 Clk = ~Clk;
	
	initial begin
		Reset_n = 0;
		uart_rx = 1;
		#201;
		Reset_n = 1;
		#200;
		uart_rx = 0;// 8'b0101_0101
		#(5208*20);
		
		uart_rx = 1;
		#(5208*20);
		uart_rx = 0;
		#(5208*20);
		uart_rx = 1;
		#(5208*20);
		uart_rx = 0;
		#(5208*20);
		uart_rx = 1;
		#(5208*20);
		uart_rx = 0;
		#(5208*20);
		uart_rx = 1;
		#(5208*20);
		uart_rx = 0;
		#(5208*20);
		
		uart_rx = 1;
		#(5208*20);
		#(5208*20);
		$stop;
	end
endmodule
		